1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the contact level of a semiconductor device, in which contact areas, such as drain and source regions, as well as gate electrode structures, are connected to the metallization system of the semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
On the basis of the field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, embedded memories and the like. Due to the reduced dimensions, the operating speed of the circuit components has been increased with every new device generation, wherein, however, the limiting factor of the finally achieved operating speed of complex integrated circuits is no longer the individual transistor element but the electrical performance of the complex wiring system, which may be formed above the device level including the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the inner-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, which connects, with one end, to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and, with another end, to a respective metal line in the metallization layer and/or to a contact region of a further semiconductor-based circuit element, in which case the interconnect structure in the contact level is also referred to as a local interconnect. The contact structure may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. Upon further shrinkage of the critical dimensions of the circuit elements in the device level, also the dimensions of metal lines, vias and contact elements have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required “packing density” in accordance with density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level have to be provided with critical dimensions on the same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically the interlayer dielectric material is formed first and is patterned so as to receive contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. In particular, in densely packed device regions, the lateral size of the drain and source areas, and thus the available area for the contact regions, is 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy.
Consequently, any misalignments during the critical contact process may result in contact failures, for instance caused by short circuits or leakage paths formed between the gate and the contact elements connecting to the drain and source regions. Furthermore, in particular in densely packed device areas, the pronounced surface topography caused by the closely spaced gate electrode structures increasingly results in deposition-related irregularities when forming the interlayer dielectric material in the narrow spaces formed between the densely packed gate electrode structures. For example, corresponding voids may be generated upon depositing the dielectric material or material system and these voids may extend along the transistor width direction, thereby forming buried channels, which in turn may be filled with a conductive material upon forming the contact openings and filling the same with the contact metal. In this case, contact elements of neighboring active regions may be “connected” by any buried tungsten channels, thereby also resulting in a severe contact failure. In order to avoid such continuous buried tungsten channels, a dielectric material liner may be deposited after forming the contact openings in order to seal the contact openings with respect to any buried voids previously created during the critical interlayer dielectric material deposition. In this case, however, the lateral dimensions of the contact openings may further be reduced, thereby increasing the overall contact resistivity. Moreover, a reliable deposition of a thin liner material into the high aspect ratio contact openings may also represent a very critical process step, which may not be compatible in sophisticated semiconductor devices in which the gate length approaches 40 nm and less.
In addition to improving transistor performance by reducing the gate length of sophisticated field effect transistors, superior material systems may also be provided in the gate electrode structures in order to provide a desired high capacitive coupling between the electrode and the channel region, without unduly increasing the leakage currents. To this end, typically, so-called high-k dielectric materials are used, which are to be understood as dielectric materials having a dielectric constant of 10.0 and higher, so that, for a given layer thickness, a significantly higher capacitive coupling may be obtained compared to a silicon oxide-based gate dielectric layer of the same thickness. Moreover, since a desired adjustment of the transistor threshold voltage may no longer be compatible with the high-k dielectric material, additional work function metal species may have to be incorporated into the gate electrode structure, for instance in the form of lanthanum, aluminum, tantalum, titanium and the like, so as to adjust the transistor characteristics for complementary transistors, or generally for transistors of different threshold voltage requirements. Moreover, by providing a metal-containing highly conductive material in close proximity to the high-k dielectric material, the creation of a depletion zone may also be avoided, as is typically the case in conventional polysilicon/silicon oxide-based gate electrode structures. It turns out, however, that incorporating the complex material systems of the gate electrode structures in an early manufacturing stage, i.e., upon actually forming the gate electrode structures, is associated with a plurality of difficulties that essentially arise from the fact that these sophisticated materials may significantly alter their characteristics when exposed to typical process conditions during the further processing of the device. Consequently, in some very promising approaches, process strategies have been developed in which the gate electrode structures may be provided as substantially conventional structures comprising polysilicon and a silicon oxide-based material, on the basis of which the basic transistor configuration is completed and, after any high temperature processes, the polysilicon material, possibly in combination with the dielectric material, is replaced by a complex material system comprising the high-k dielectric material, the work function metal species and typically a highly conductive electrode metal, such as aluminum and the like. In such replacement gate approaches, typically, a portion of the interlayer dielectric material is provided in order to passivate the transistors during the replacement of a polysilicon material, a top surface of which is exposed during a complex removal process. After the removal of the silicon material and the incorporation of the desired material system, a contact regime is applied which has to take into account the high-k metal gate electrode structure and the corresponding manufacturing requirements. Consequently, the critical process of forming contact elements may have to be compatible with a replacement gate approach when forming semiconductor devices comprising a highly complex logic circuit portion.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which contact structures may be formed so as to comply with the requirements of a replacement gate approach, while additionally avoiding or at least reducing the effects of one or more of the problems identified above.